#ifndef __IMAX6ULL_H__
#define __IMAX6ULL_H__

#include <stdio.h>
#include <string.h>
#include <stdint.h>

#define CCM_BASE (0x020c4000)
#define CCM_ANALOG_BASE (0x020c8000)
#define IOMUX_SW_MUX_BASE (0x020E0014)
#define IOMUX_SW_PAD_BASE (0x020e0204)
#define GPIO1_BASE (0x0209c000)
#define GPIO2_BASE (0x020A0000)
#define GPIO3_BASE (0x020A4000)
#define GPIO4_BASE (0x020A8000)

// CCM 外设
typedef struct
{
    volatile uint32_t CCR;
    volatile uint32_t CCDR;
    volatile uint32_t CSR;
    volatile uint32_t CCSR;
    volatile uint32_t CACRR;
    volatile uint32_t CBCDR;
    volatile uint32_t CBCMR;
    volatile uint32_t CSCMR1;
    volatile uint32_t CSCMR2;
    volatile uint32_t CSCDR1;
    volatile uint32_t CS1CDR;
} CCM_Type;

// CCM_ANALOG 外设
typedef struct
{
    volatile uint32_t PDR0;
} CCM_ANALOG_Type;

// IOMUX_SW_MUX 外设
typedef struct
{
    volatile uint32_t NAND_DQS;

    volatile uint32_t CSI_CMD;
    volatile uint32_t CSI_CLK;
    volatile uint32_t CSI_DATA0;
    volatile uint32_t CSI_DATA1;
    volatile uint32_t CSI_DATA2;
    volatile uint32_t CSI_DATA3;
    volatile uint32_t CSI_MCLK;
    volatile uint32_t CSI_PIXCLK;
    volatile uint32_t CSI_VSYNC;
    volatile uint32_t CSI_HSYNC;
    volatile uint32_t CSI_DATA00;
    volatile uint32_t CSI_DATA01;
    volatile uint32_t CSI_DATA02;
    volatile uint32_t CSI_DATA03;
    volatile uint32_t CSI_DATA04;
    volatile uint32_t CSI_DATA05;
    volatile uint32_t CSI_DATA06;
    volatile uint32_t CSI_DATA07;

} IOMUX_SW_MUX_Type;

// IOMUX_SW_PAD 外设
typedef struct
{
    volatile uint32_t DRAM_ADDR00;
    volatile uint32_t DRAM_ADDR01;
    volatile uint32_t DRAM_ADDR02;
    volatile uint32_t DRAM_ADDR03;
    volatile uint32_t DRAM_ADDR04;
    volatile uint32_t DRAM_ADDR05;
    volatile uint32_t DRAM_ADDR06;
    volatile uint32_t DRAM_ADDR07;
    volatile uint32_t DRAM_ADDR08;
    volatile uint32_t DRAM_ADDR09;
    volatile uint32_t DRAM_ADDR10;
    volatile uint32_t DRAM_ADDR11;
    volatile uint32_t DRAM_ADDR12;
    volatile uint32_t DRAM_ADDR13;
    volatile uint32_t DRAM_ADDR14;
    volatile uint32_t DRAM_ADDR15;
    volatile uint32_t DRAM_DQM0;
    volatile uint32_t DRAM_DQM1;
    volatile uint32_t DRAM_RAS_B;
    volatile uint32_t DRAM_CAS_B;
    volatile uint32_t DRAM_CS0_B;
    volatile uint32_t DRAM_CS1_B;
    volatile uint32_t DRAM_SDWE_B;
    volatile uint32_t DRAM_ODT0;
    volatile uint32_t DRAM_ODT1;
    volatile uint32_t DRAM_SDBA0;
    volatile uint32_t DRAM_SDBA1;
    volatile uint32_t DRAM_SDBA2;
    volatile uint32_t DRAM_SDCKE0;
    volatile uint32_t DRAM_SDCKE1;
    volatile uint32_t DRAM_SDCLK0_P;
    volatile uint32_t DRAM_SDQS0_P;
    volatile uint32_t DRAM_SDQS1_P;
    volatile uint32_t DRAM_RESET;

    volatile uint32_t TEST_MODE;

    volatile uint32_t JTAG_TRST_B;

    volatile uint32_t GPIO1_IO00;
    volatile uint32_t GPIO1_IO01;
    volatile uint32_t GPIO1_IO02;
    volatile uint32_t GPIO1_IO03;
    volatile uint32_t GPIO1_IO04;
    volatile uint32_t GPIO1_IO05;
    volatile uint32_t GPIO1_IO06;
    volatile uint32_t GPIO1_IO07;
    volatile uint32_t GPIO1_IO08;
    volatile uint32_t GPIO1_IO09;

    volatile uint32_t UART1_TX_DATA;
    volatile uint32_t UART1_RX_DATA;
    volatile uint32_t UART1_CTS_B;
    volatile uint32_t UART1_RTS_B;
    volatile uint32_t UART2_TX_DATA;
    volatile uint32_t UART2_RX_DATA;
    volatile uint32_t UART2_CTS_B;
    volatile uint32_t UART2_RTS_B;
    volatile uint32_t UART3_TX_DATA;
    volatile uint32_t UART3_RX_DATA;
    volatile uint32_t UART3_CTS_B;
    volatile uint32_t UART3_RTS_B;

    volatile uint32_t LCD_HSYNC;
    volatile uint32_t LCD_VSYNC;
    volatile uint32_t LCD_RESET;
    volatile uint32_t LCD_DATA00;
    volatile uint32_t LCD_DATA01;
    volatile uint32_t LCD_DATA02;
    volatile uint32_t LCD_DATA03;
    volatile uint32_t LCD_DATA04;
    volatile uint32_t LCD_DATA05;
    volatile uint32_t LCD_DATA06;
    volatile uint32_t LCD_DATA07;
    volatile uint32_t LCD_DATA08;
    volatile uint32_t LCD_DATA09;
    volatile uint32_t LCD_DATA10;
    volatile uint32_t LCD_DATA11;
    volatile uint32_t LCD_DATA12;
    volatile uint32_t LCD_DATA13;
    volatile uint32_t LCD_DATA14;
    volatile uint32_t LCD_DATA15;
    volatile uint32_t LCD_DATA16;
    volatile uint32_t LCD_DATA17;
    volatile uint32_t LCD_DATA18;
    volatile uint32_t LCD_DATA19;
    volatile uint32_t LCD_DATA20;
    volatile uint32_t LCD_DATA21;
    volatile uint32_t LCD_DATA22;
    volatile uint32_t LCD_DATA23;

    volatile uint32_t NAND_RE_B;
    volatile uint32_t NAND_WE_B;
    volatile uint32_t NAND_DATA00;
    volatile uint32_t NAND_DATA01;
    volatile uint32_t NAND_DATA02;
    volatile uint32_t NAND_DATA03;
    volatile uint32_t NAND_DATA04;
    volatile uint32_t NAND_DATA05;
    volatile uint32_t NAND_DATA06;
    volatile uint32_t NAND_DATA07;
    volatile uint32_t NAND_ALE;
    volatile uint32_t NAND_WP_B;
    volatile uint32_t NAND_READY_B;
    volatile uint32_t NAND_CE0_B;
    volatile uint32_t NAND_CE1_B;
    volatile uint32_t NAND_CLE;
    volatile uint32_t NAND_DQS;

    volatile uint32_t SD1_CMD;
    volatile uint32_t SD1_CLK;
    volatile uint32_t SD1_DATA0;
    volatile uint32_t SD1_DATA1;
    volatile uint32_t SD1_DATA2;
    volatile uint32_t SD1_DATA3;
    volatile uint32_t CSI_MCLK;
    volatile uint32_t CSI_PIXCLK;
    volatile uint32_t CSI_VSYNC;
    volatile uint32_t CSI_HSYNC;
    volatile uint32_t CSI_DATA00;
    volatile uint32_t CSI_DATA01;
    volatile uint32_t CSI_DATA02;
    volatile uint32_t CSI_DATA03;
    volatile uint32_t CSI_DATA04;
    volatile uint32_t CSI_DATA05;
    volatile uint32_t CSI_DATA06;
    volatile uint32_t CSI_DATA07;

    volatile uint32_t GRP_ADDDS;
    volatile uint32_t GRP_DDRMODE_CTL;
    volatile uint32_t GRP_B0DS;
    volatile uint32_t GRP_DDRPK;
    volatile uint32_t GRP_CTLDS;
    volatile uint32_t GRP_B1DS;
    volatile uint32_t GRP_DDRHYS;
    volatile uint32_t GRP_DDRPKE;
    volatile uint32_t GRP_DDRMODE;
    volatile uint32_t GRP_DDR_TYPE;

} IOMUX_SW_PAD_Type;

// GPIO 外设
typedef struct
{
    volatile uint32_t DR;
    volatile uint32_t GDIR;
    volatile uint32_t PSR;
    volatile uint32_t ICR1;
    volatile uint32_t ICR2;
    volatile uint32_t IMR;
    volatile uint32_t ISR;
    volatile uint32_t EDGE_SEL;

} GPIO_Type;

// 外设指针
#define CCM ((CCM_Type *)CCM_BASE)
#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
#define IOMUX_SW_MUX ((IOMUX_SW_MUX_Type *)IOMUX_SW_MUX_BASE)
#define IOMUX_SW_PAD ((IOMUX_SW_PAD_Type *)IOMUX_SW_PAD_BASE)
#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
#define GPIO4 ((GPIO_Type *)GPIO4_BASE)

#endif